****************************************************
*	Autor 	: Yao Gang 
*	Date  	: July. 22 2004							     
*	Version : 1.1
*	E-mail  : y.gang@ed.ac.uk
*	Company : University of Edinburgh
*	Project : 0.25um technology cmos 6-T sram
***************************************************

**********************************
*     Device models     	 *
**********************************
*.lib '..\models\cmos25_level49.txt'	ff  
.include '..\models\manual.txt'  
*.include '..\models\cmos25_level49.txt'
* cell library description
*.model pmos pmos level=43
*.model nmos nmos level=43


**********************************
*     Control and measurements   *
**********************************
.options list node post=2
.tran 200p 120n
.op
.print tran v(wordline) v(bitline) v(a2) v(a1) 
*.print dc i(a2) i(a1)
*.measure tran t_delay TRIG v(in) VAL=1.65 CROSS=1 TARG v(out) VAL=1.65 CROSS=1
.measure  tran avg_current   avg i(vdd) FROM=20n	TO=40n
.measure  avg_power   PARAM='avg_current*2.5'

*********************************
*     circuits and stimulus     *
*********************************

* circuit netlist description
m1 a1  a2 vdd1   vdd1 pmos l=.25u   w=.5u
m2 a1  a2 0     0   nmos l=.25u 	 w=.25u
m3 a2  a1 vdd2   vdd2 pmos l=.25u   w=.5u
m4 a2  a1 0     0   nmos l=.25u 	 w=.25u
* pass transistor enable 
m5 bitline  	wordline a1 		 0	nmos l=.25u   w=2u
m6 a2  		wordline invbitline   	 0	nmos l=.25u   w=2u

cbitload1	bitline			0	1p
cbitload2	invbitline		0	1p
*source
vdd1 vdd1 0 2.5 
vdd2 vdd2 0 2.5 
*wordline
vwl wordline  0  pulse .1 2.5 2n 2n 2n 6n 20n
*bitline
*write "0"----->write "1"---->write "0"
vblp 	bitline     0  pulse 0.0 2.5 20n 2n 2n 20n 40n
vbln 	invbitline  0  pulse 2.5 .0 20n 2n 2n 20n 40n

.end
